The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 1986
Filed:
Dec. 06, 1984
Walter L Davis, Coral Springs, FL (US);
Yolanda Prieto, Miami, FL (US);
George W Smoot, Sunrise, FL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
An interface circuit is coupled between the last stage of an FSK receiver and a limiter to provide a biasing voltage signal to the limiter. The receiver includes a power saver circuit which supplies power on an interrupted basis. The interface circuit contains maximum and minimum detectors which derive and hold voltages corresponding to the maximum and minimum values of the discriminated signal from the receiver. These maximum and minimum corresponding voltages are averaged in a predetermined manner to provide the biasing voltage to the limiter. Thus, a proper bias voltage level can be accurately and quickly determined, and supplied to the limiter when power is supplied.