The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 1986

Filed:

Feb. 11, 1985
Applicant:
Inventors:

Lawrence C Barnes, Apopka, FL (US);

Robert G Mankedick, Longwood, FL (US);

Assignee:

NCR Corporation, Dayton, OH (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
358149 ; 358 22 ;
Abstract

An apparatus, and its method, for overlaying a computer display on a video signal, having a video signal receiving circuit, a sync strip circuit connected to said video signal receiving circuit for stripping the sync pulses from the video signal, and a display control circuit for generating display control pulses. A phase locked loop circuit is provided for locking the display control pulses in phase with sync pulses stripped from the video signal when the video signal is present, and for controlling the display control means to generate display control pulses at a selected rate when the video signal is absent. A vertical drive pulse generating circuit generates vertical drive pulses in phase with selected ones of the sync pulses stripped from the video signal when the video signal is present, and generates vertical drive pulses after a set number of generated display control pulses when the video signal is absent. A computer display generator circuit generates computer display signals under the control of the display control pulses and the vertical drive pulses. A combining circuit combines the video signal with the generated computer display signals when the video signal is present, and blocks the subsequent combining of later received video signals with the generated computer display signals for a set time when the video signal is absent, allowing the phase locked loop circuit to lock the display control pulses in phase with the sync pulses of the reestablished, later received video signals.


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