The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 1986
Filed:
Dec. 12, 1984
Dennis J Kayser, Hudson, NH (US);
Wang Laboratories, Inc., Lowell, MA (US);
Abstract
A power switching means for connecting a power source to a digital data processing system. The switching means includes a power switch for connecting the power source to the system and two control switches. A first control switch determines whether system power is to be turned on or off and is responsive to a turn-on selection signal to provide an initial turn-on signal to the power switch if a power turn-on is to be performed. The second control switch is responsive to a power turn-on/turn-off initialization signal to initiate and control the turn-on and turn-off operations. The second control switch is responsive to the initialization signals at power turn-on to enable the first control switch to be responsive to a power-on selection signal to provide the initial turn-on signal to the power switch. The second control switch thereafter provides a sustaining signal to the power switch during the period in which power is to be provided to the system and is responsive a subsequent initialization signal to terminate the sustaining signal to the power switch, thereby turning off system power. The power switching means further includes a current limiter connected between the power source and the system to limit inrush current during power turn-on and the second switch further includes a bypass switch for providing a low resistance path around the current limiting means during system power on state.