The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 1986

Filed:

Dec. 18, 1984
Applicant:
Inventor:

William G Crouse, Raleigh, NC (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04Q / ;
U.S. Cl.
CPC ...
34082505 ; 307571 ; 178 / ;
Abstract

A solid state switching network includes three FET switches or devices arranged in a substantially 'T' (or inverted 'T') configuration. The network is controlled so that in an 'OFF' or non-conducting state two of the FET switches are 'OFF' and one is on. The high 'OFF' impedance of the two FETs work against the low 'ON' impedance of the third FET to provide an open circuit between the input and output of the switching network. The open circuit has greater isolation than is feasible with conventional circuits. The switching network or module is used in several configurations to couple data terminal equipment (DTE) to a communications highway.


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