The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 1986
Filed:
May. 17, 1984
Ronald L Cline, Monte Sereno, CA (US);
John G Campbell, Los Altos, CA (US);
Fairchild Semiconductor Corporation, Cupertino, CA (US);
Abstract
A circuit technique for eliminating history-dependent skew and distortion of signals as they propagate through multiple gate stages in critical timing paths. It has been discovered that spurious effects can be attributed to signal coupling between stages, and that such coupling may be reduced by providing separate threshold voltage supplies for the critical gates. Each of the first and second gate stages comprises first and second transistors having their respective emitters coupled to a common circuit point, a current source coupled to the common circuit point to provide current flow through the transistors, with the relative current flow through said transistors being determined by the relative voltage levels at the respective bases. The output signal is taken from the collector of one of the transistors. First and second threshold voltage sources are coupled to the respective bases of the second transistors of the first and second gate stages. The threshold voltage sources are isolated from one another such that current drawn from either results in substantially no change in the voltage delivered by the other. This circuit technique has applicability to configurations where the first and second gate stages are cascaded and to configurations where the gate stages are parallel stages in different branches of the signal path.