Monolithic delta frame circuit

Abstract

A monolithic delta frame circuit comprises a high speed line address circuit, demultiplexer, line shift register, plurality of buffer amplifiers, an array of difference frame elements, reset circuit means, plurality of sample and hold circuits, multiplexer, and a high speed line address circuit. The high speed line address circuit clocks a single line video input at a fast rate into the demultiplexer for demultiplexing into the line shift register, the line shift register shifts the single line signals and noise into the elements of the array of difference frame elements. As the data from the previous frame which consists of noise or noise minus signal is still present in the difference elements only the signal or delta signal portion feeds through a reset circuit at a slower rate to the multiplexer. The reset circuit introduces offset noises into the signal which is substantially reduced by feedback through the reset circuit. The high speed line address register is connected to the multiplexer for controlling the video output signals through the video out terminal. The video output is at the fast rate, to reduce this rate and for minimizing display blind time the sample and hold circuits are introduced between the reset circuit and the multiplexer. Thus the monolithic delta frame may be used to remove reset noise and rate conversion or in tandem to remove reset noise and offset noise as well as rate conversion.