Pillar via process

Abstract

A method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits while at the same time exposing other large area contact regions such as a bonding pad. A first conductor layer is formed on the device substrate, etched to delineate the bonding pad and the first level interconnects, and covered with a differentially etchable intermediate conductive material which is delineated to form the conductive pillar. A dielectric planarizing layer is applied so as to have a smooth surface contour and a lower thickness above the conductive pillar than over the first level interconnects or the bonding pad. The planarizing dielectric is desirably a negative acting radiation sensitive material such as a polyimide. A mask is used to render the portions of this dielectric planarizing layer above the bonding pad soluble so that it may be dissolved away while leaving the remainder undisturbed. The resulting structure is then blanket etched to remove the smaller thickness of dielectric layer above the top of the pillar. The dielectric surface and pillar surface smoothly join. Another conductive layer is then applied over the surface of the dielectric planarizing layer and in contact with the top of the pillar and patterned in the conventional manner to form the second level interconnects. The resulting structure has a relatively smooth surface topology and little or no step at the pillars.