The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 1986

Filed:

Aug. 12, 1985
Applicant:
Inventor:

Ronald W Russell, Sunnyvale, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F / ;
U.S. Cl.
CPC ...
330256 ; 330260 ; 330289 ;
Abstract

A JFET operational amplifier input stage is disclosed along with am offset potential trimming circuit. The trimming circuit includes a scaled down compensation stage that is modeled after the input stage and provided with a constant temperature independent bias. This generates a trimming current that varies with temperature inversely with the transconductance of the input stage. A control circuit applies a digitally controlled portion of the trimming current to the input stage so as to compensate the offset potential. The input offset potential is therefore compensated without changing the offset potential temperature drift. Desirably the compensation is achieved after device assembly.


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