Logic for calculating bit error rate in a data communication system

Abstract

A system for determining the bit error rate in a communication system comprising logic for generating a stream of data bits, bit extracting logic for periodically extracting N consecutive bits after the occurrence of every Mth bit, where the N consecutive bits are divided into a group of A bits and a group of C bits, where A and C are equal integers, and a single B bit is positioned between the group of A and C bits, where M>>A, where the N bits can be any combination of binary 1's and 0's. Logic extracts and stores a finely quantized sample of the B bit of each group of N bits. An adder adds an auxiliary group of X bits to the N bits to form a memory address consisting of A, B, C, and X bits. A plurality of memories each has storage locations for a single finely quantized B bit sample. Each memory further is selectable by a unique combination of the binary bits A+B+C with any given storage location in each memory being accessible by various combinations of the X bits. Appropriate logic by a predetermined algorithm calculates the current probability of bit rate error.