High speed address calculation circuit for a pipeline-control-system

Abstract

A high speed address calculation circuit for a pipeline-control-system data-processing apparatus includes an instruction register, a register file, an address register, a first data selector, an increment register, a second data selector, a decoder, an adder and a third data selector. The instruction register stores instructions from a memory, and the register file is addressed by the register designation data of the instructions stored in the instruction register. The address register stores an operand address, and the increment register stores increment data calculated in an arithmetic unit. The first data selector selects either the address from the address register or the data from the register file, and the second data selector selects either the data from the increment register or the destination field data included in each instruction. The decoder generates a signal to specify the data to be selected by the first and second data selectors. The adder receives data from the first and second selectors and provides an operand address. The third data selector receives the operand address from the adder and the address generated by the arithmetic unit, selects one of these addresses, and transfers the selected address to the address register.