Phase-locked loop with switchable phase detector

Abstract

A phase-locked loop has a phase detector and a clock pulse oscillator. The phase detector multiplies a received reference signal by a comparison signal. It is constituted by a plurality of signal channels 207 each receiving the reference signal and having a cascade arrangement of a switching circuit 208 and a weighting network 209. The switching circuit is controlled by one or more sequences of main control pulses supplied by a pulse distributor circuit receiving clock pulses. Each signal channel has a constant weighting factor. For the k.sup.th signal channel the weighting factor is equal to the signal sample n(t.sub.o +kT.sub.s) of a fundamental signal n(t) which has a fundamental frequency f.sub.o. T.sub.s is the reciprocal of the clock pulse frequency f.sub.s. For each sequence of main control pulses controlling the switching circuit in the k.sup.th signal channel, this signal channel produces a main signal z(k, t). The main signals supplied by all the signal channels are added together. To allow locking of the loop on frequencies which are an integral multiple p of the fundamental frequency, the clock pulse oscillator has a frequency f.sub.s which is an integral multiple N of the fundamental frequency. In addition, the pulse distributor circuit has an input for setting the parameter p and at least N distributor outputs to which the several clock pulses are applied. More specifically, the clock pulse having number n is applied to the distributor output having number np modulo N. The sequence of pulses thus occurring at these distributor outputs constitutes the sequence of main control pulses.