The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 1986
Filed:
Apr. 29, 1985
Masahisa Suzuki, Sagamihara, JP;
Takashi Mimura, Machida, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
A semiconductor device, which comprises an E-mode FET and a D-mode FET and utilizes a two-dimensional electron gas, comprises a semi-insulating semiconductor substrate, a channel layer, an electron-supply layer, a third layer, a first etching-stoppable layer, a fifth layer, and a second etching-stoppable layer, which layers are formed in sequence on the substrate. An etching process for forming grooves of gate electrodes of the FETs comprises a first etching treatment removing the first etching-stoppable layer portion in the E-mode FET region and the second etching-stoppable layer portion in the D-mode FET region, and a second etching treatment removing the third layer portion in the E-mode FET region and the fifth layer portion and using an etchant different from that used in the first etching treatment. In the second etching treatment, reactive ion etching method using a CCl.sub.2 F.sub.2 etchant gas is adopted, since GaAs can be thereby rapidly etched as compared with AlGaAs used for the etching-stoppable layer material.