Teletext receiver

Abstract

A teletext receiver incorporating a demodulation circuit, a data demultiplexing circuit, a memory, a microprocessor and a numbering keyboard. The inventive receiver also comprises an early article acquisition decision circuit disposed between the demultiplexing circuit and the memory. This circuit incorporates a shift register with five cells, a storage module having a first group of three storage cells able to store three bytes, a second group of three storage cells able to store three bytes, a two-bit flip-flop, a logic comparison circuit incorporating a first group of three byte comparators, a second group of three byte comparators, an article start code detector, and a comparison synthesis logic circuit connected to the six byte comparators, to the detector and to the flip-flop. This circuit supplies an opening or closing control signal applied to the control input of the memory. The microprocessor loads in an appropriate manner the storage cells with bytes defining a page to be selected and bytes defining a threshold, such that all the articles whose classification bytes exceed this threshold, bring about the appearance of the memory opening signal. The microprocessor checks after each data transmission cycle the state of the memory in order to raise or lower the threshold, or leave it unchanged.