The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 1986

Filed:

Nov. 09, 1982
Applicant:
Inventors:

Graham Shenton, Monte Sereno, CA (US);

Ioan G Jones, Los Gatos, CA (US);

David W Lucas, Saratoga, CA (US);

Ronald E Barton, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364490 ; 364488 ; 364491 ;
Abstract

A method of designing an integrated circuit layout based on primitive elements such as transistors, resistors, and conductors and cell structures formed from the primitive functional element. The primitive elements are defined by surface dimensions, semiconductor construction, and surface layers and can be placed to accommodate special cell structures and functions. Design time can be minimized by using preexisting cell structures stored in suitable computer means, or layout surface and production costs can be minimized by designing new cell structures using a simple technique. Process independence can be achieved by having a complete design based on a small number of primitive elements which can be readily modified.


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