The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 1986

Filed:

Jul. 11, 1984
Applicant:
Inventor:

Richard J Starke, Temple, PA (US);

Assignee:

AT&T Bell Laboratories, Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
377 72 ; 377 76 ; 377117 ; 377126 ; 377129 ;
Abstract

A CMOS dynamic circulating-one shift register (10) is disclosed. One stage of a conventional N-stage circulating-one shift register is modified to become a control cell (14) which performs two additional functions, referred to as AUTOSET and AUTOCLEAR, to guarantee the existence of a single circulating logic one, after power up or during long-term use. To perform the AUTOCLEAR function, the output (Q3) of the control cell is connected to the CLR inputs of each of the remaining stages (12.sub.1 -12.sub.N-1) comprising the shift register. Therefore, when Q3 becomes a logic one, the remaining Q outputs are automatically cleared. The Q output from the control cell is also fed back as the D input to the first stage of the shift register (12.sub.1) to continue the circulation process. In relation to the AUTOSET function, the Set outputs from each stage of the shift register are coupled together and applied as an input to the control cell, which performs a wired 'OR' operation between the Set outputs and the current D input to the control cell to provide a Q output of logic one from the control cell if and only if all of the Q outputs from each of the remaining stages are equal to a logic zero.


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