The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 1986

Filed:

Jun. 28, 1984
Applicant:
Inventors:

Ernest N Levine, Poughkeepsie, NY (US);

Lewis D Lipschutz, Poughkeepsie, NY (US);

Horatio Quinones, Peekskill, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B23K / ;
U.S. Cl.
CPC ...
228123 ; 228122 ; 228124 ; 2281802 ; 228231 ;
Abstract

In accordance with the present invention, we provide a new method for relieving stresses in the device-substrate interconnection structure which greatly enhances the resistance of the interconnection solder bonds to fatigue failure. In accordance with the aforementioned object of the process of our invention for forming improved solder interconnections between integrated circuit semiconductor devices and the supporting substrate, the process includes the step of joining the device I/O pads to the corresponding I/O pads of the substrate by positioning the device over the substrate with solder material selectively positioned between the respective I/O pads, heating the assembly to at least the melting point of the solder material, and cooling to solidify the solder. Subsequently, the resultant device-substrate is annealed by heating to an annealing temperature in the range of 115.degree. to 135.degree. C. and maintaining this temperature for a time in excess of 2 days.


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