The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 1986
Filed:
Aug. 26, 1985
Robert R Whitlock, College Park, MD (US);
Nicolas A Papanicolaou, Silver Spring, MD (US);
The United States of America as represented by the Secretary of the Navy, Washington, DC (US);
Abstract
A line imager comprising: a semiconductor body; a planar, transparent piezoelectric body having a main surface overlying and in proximity to the semiconductor body; wave propagation means for propagating acoustic waves on the main surface of the piezoelectric body to create traveling potential wells in the underlying semiconductor body; a traveling potential well path located in the semiconductor, the traveling potential well path beginning at the wave propogation means and extending straight away therefrom; semiconductor depletion means for depleting the semiconductor of majority charge carriers along the traveling potential well path, the depletion means located atop the piezoelectric body; a gate located on the semiconductor body and alongside and parallel to the traveling potential well path and adjoining the semiconductor depletion means; a plurality of sensor pixels for accumulating charge, the sensor pixels located in the semiconductor body, the pixels aligned next to each other and running parallel to, alongside and overlapping the gate so the integrated charge in each sensor pixel will proceed into their respective traveling potential wells when the potential across the gate is lowered, the gate having length at least equal to the length of the plurality of sensor pixels; and a dump gate located on the semiconductor and parallel to and overlapping the plurality of sensor pixels, the plurality of sensor pixels being situated between the dump gate and the gate, the dump gate causing the charge integrated in the plurality of sensor pixels to flow to ground when the potential across the dump gate is lowered, the dump gate being at least as long as the length of the plurality of sensor pixels.