Bit steering apparatus and method for correcting errors in stored data,

Abstract

In a computer system, an apparatus detects the existence of an error in data retrieved from memory, corrects the erroneous data, and takes steps to maintain the correct condition of the data. In taking these steps, when the erroneous data is corrected, the corrected data is stored in a spare portion of the memory; however, the address of the corrected data in memory is recorded in a bit steering array, a physically separate memory of much smaller size. The bit steering array stores a plurality of such addresses. When an incoming read request signal is generated, it simultaneously energizes the memory and the bit steering array. In response to the read request signal, the bit steering array develops an output signal indicative of the address of the corrected data and representative of the identity of the erroneous data. In response to the read request signal, data, including the erroneous data, is read from memory. In addition, the corrected data is read from the spare portion of the memory. However, in response to the output signal from the bit steering array, the erroneous data is replaced or exchanged with the corrected data. In the case of a double bit error, one bit is corrected in the manner just described. The other bit is corrected in an error correction code matrix, which is designed to correct single bit errors.