The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 1986
Filed:
Mar. 14, 1984
George Knoedl, Jr, Mt. Pleasant, NJ (US);
AT&T Bell Laboratories, Murray Hill, NJ (US);
Abstract
A dual-clock, edge triggered, flip-flop circuit wherein one set of outputs responds to two independent inputs without giving rise to indeterminate states regardless of the combination of inputs comprising a first pair of gates (1-2 or 11-12) cross-coupled to form a first trigger flip-flop. A second pair of gates (7-8 or 17-18) are cross-coupled to form a second trigger flip-flop. A third pair of gates (4-5 or 14-15) are cross-coupled to form an output flip-flop having set and reset terminals and a pair of output terminals. A gate (3 or 13) is coupled from the output of the first trigger flip-flop to the set terminal of the output flip-flop, the input to the first trigger flip-flop also being coupled to the input of this latter gate. Another gate (6 or 16) is coupled from the output of the second trigger flip-flop to the reset terminal of the output flip-flop, the input to the second trigger flip-flop also being coupled to the input of this gate. Each output terminal is cross-coupled back to the input of a respective one of the trigger flip-flops to 'disarm', or reset, the same after the output flip-flop has changed state.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile