The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 1986
Filed:
Mar. 25, 1985
Craig A Armiento, Burlington, MA (US);
Peter E Norris, Cambridge, MA (US);
GTE Laboratories Incorporated, Waltham, MA (US);
Abstract
Method of fabricating a monolithic integrated circuit structure incorporating a complementary pair of GaAs/AlGaAs modulation-doped field effect transistors (MODFET's) including providing a substrate of semi-insulating GaAs, depositing an epitaxial layer of undoped AlGaAs on its surface, and ion-implanting a heavily doped N-type donor region and a heavily doped P-type acceptor region in the undoped AlGaAs. A thin spacer layer of undoped AlGaAs is epitaxially deposited on the previously deposited AlGaAs layer, and an epitaxial layer of undoped GaAs is deposited on the spacer layer. First and second gate members which form Schottky barriers with the GaAs are placed on the GaAs layer overlying portions of the N-type donor region and P-type acceptor region, respectively. N-type source and drain zones are formed in the GaAs layer on opposite sides of the first gate member, and P-type source and drain zones are formed in the GaAs layer on opposite sides of the second gate member. A first MODFET is provided by the N-type donor region, the N-type source and drain, the region of undoped GaAs between the source and drain which form a two-dimensional electron gas region, and the first gate member. A second MODFET complementary to the first is provided by the P-type acceptor region, the P-type source and drain, the region of undoped GaAs between the source and drain which form a two-dimensional hole gas region, and the second gate member.