High-speed sequential serial manchester decoder

Abstract

An incoming serial Manchester signal is synchronously sampled by a first flip-flop with respect to a reference clock signal of a frequency f.sub.o. A second flip-flop divides the reference clock signal to provide f.sub.o /2 clocking to a pair of shift registers wherein one shift register is of bit length M and the other is of bit length N. The first flip-flop provides to the first shift register a present sample corresponding to the state of the Manchester waveform. A third flip-flop samples and stores the state of the Manchester waveform sample, as provided by the first flip-flop, which occurred one-half clock period prior to the f.sub.o /2 clocking of the shift registers. The third flip-flop provides to the second shift register a delayed sample corresponding to the state of the Manchester waveform. The sample provided to the second shift register is a sample which occurred previously in time, by 1/f.sub.o clock period, relative to the present sample provided to the first shift register. Sample pairs are stored and shifted at the rate of f.sub.o /2 while a sampling rate of f.sub.o is achieved. As a result, the interval over which the sample at each register bit output remains stable is increased, thereby enabling the use of a sequential decoding technique. The outputs of the two shift registers are interleaved, and tied to the inputs of a programmable gate array, to synthesize a single shift register of bit length M+N. State machine Boolean expressions encoded into the gate array are utilized to sequentially recover data, clock and gap signals and to facilitate self-test diagnostics.