The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 1986
Filed:
Dec. 23, 1983
Applicant:
Inventor:
Tsuneo Kinoshita, Tokyo, JP;
Assignee:
Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364491 ; 307303 ; 364300 ;
Abstract
A gate array is used as the base component of a custom-circuit LSI. A number of logic cells are arranged in the form of a matrix in the first area of the gate array. These logic cells are interconnected by a metal pattern or patterns to build a custom-circuit. Driver cells for energizing the output and input signals of the custom-circuit are formed in the second area of the gate array. Bonding pads, which will be used as the input/output terminals of the custom-circuit, are formed in the third area of the gate array.