Read only memory circuit

Abstract

A non-volatile integrated circuit memory is provided having an array of memory elements selectively programmable to store complimentary binary data, each one of such memory elements being formed in a different region of the integrated circuit and having an address terminal, an output terminal, a ground terminal, and a power supply terminal. Those memory cells programmed into a first logical state are provided with transistor action between the output terminal and the power supply terminal and are inhibited from having transistor action between the output terminal and the ground terminal. Conversely, those memory cells programmed to store the complementary logic state are inhibited from having transistor action between the output terminal and the power supply terminal and are provided with transistor action between the ground terminal and the output terminal. In either programmed state, the transistor action is controlled by signals fed to the address terminal of the cells. With such arrangement, since transistor action is prevented between the power supply terminal and the ground terminal of each cell, an electrical open-circuit is always present to the power supply with the result that a precharge cycle is not required during memory addressing to reduce power. The elimination of such pre-charge cycle thereby eliminates the time delays inherent with the precharge cycle circuitry to thereby increase the operating speed of the memory and, further, the elimination of the circuitry increases the storage capacity of the ROM by making more chip area available for memory cells.