N-bit digitally controlled phase shifter

Abstract

A n-bit digitally controlled phase shifter for controlling the phase of an applied signal over the range of 0.degree. to 360.degree. includes n, cascade interconnected phase shifter stages. Each phase shifter stage is formed on a semi-insulating substrate having a pair of field effect transistors and a pair of transmission lines formed thereon. Each field effect transistor (FET), includes a pair of gate electrodes, a drain electrode, and a source electrode, connected in a common (grounded) source configuration. Each transmission line is coupled between a corresponding one of the drain electrodes and a common output port. The lengths of the transmission lines are selected to provide two paths having an electrical pathlength corresponding to a phase shift of .phi..sub.1 or a phase shift of .phi..sub.1 +.DELTA..phi..sub.1 where .DELTA..phi..sub.i is the phase shift increment of the i.sup.th stage. A first one of the gate electrodes of each field effect transistor is fed by the applied signal. A pair of control signals representative of one of the bits, and its compliment, is fed to the second gate electrodes of the field effect transistors, and is used to selectively couple the applied signal to one of the drain electrodes of such field effect transistors. The phase of the applied signal is shifted by propagation through the transmission line selected through control signals. Each one of the n stages, has a predetermined electrical pathlength difference for providing a selected phase shift increment (.DELTA..phi..sub.i).