The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 1986

Filed:

Jan. 22, 1985
Applicant:
Inventors:

Michael A Damiano, Germantown, WI (US);

Dennis M Kramer, Brookfield, WI (US);

Richard F Schmerda, Oak Creek, WI (US);

Assignee:

Eaton Corporation, Cleveland, OH (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
323351 ; 307571 ;
Abstract

A solid state DC power control system having a single N-type or N-channel or majority carrier solid state switching element (Q1) connected to the high side (L) of the power supply for energizing a ground or neutral (V.sub.o) connected load (LD). A voltage level translation circuit (2,2') supplies a floating regulated control voltage to the switching element (Q1) high enough to maintain it turned on even if the voltage at the low side of the switching element (Q1) rises up to or near the supply voltage thereby allowing use of such N-type switching device (Q1) in the high side (L) of the supply. A zener diode (ZD3) limits the gate(G)-to-source(S) voltage to the proper level. A non-inverting drive circuit (10,12) controlled by a logic level signal input element (Q2) controls connection of the high voltage to the switching (Q1) gate (G). A first version uses a DC-DC converter (CON) and a preferred version uses a voltage multiplier (VM) in the voltage level translation, high voltage, gate supply circuit (2,2').


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