Semiconductor memory with redundant column circuitry

Abstract

A redundant column circuit includes a row shared predecoder (12) and predecoders (16), (18) and (20). The predecoders (16-20) are input to a one-of-sixty-four decoder (28) for providing sixty-four decoded outputs therefrom, each of which is input to a one-of-four multiplexer (30). Each of the multiplexers (30) selects one of four normal decode outputs and one of four redundant decode outputs. The selected decode output is determined by the four outputs from the row shared predecoder (12). A switch bank (32) of single pole double throw switches selects between a normal and a redundant output with the redundant output having the address associated therewith incremented by one. The output of the switches in the bank (32) is input to the deactivation circuits (36) for output therefrom to a memory array (38). The memory array (38) has a redundant column (R) in parallel therewith which is controlled by the first switch in a the switch bank (32). When a defective column is replaced, all of the switches between the redundant column and the defective column have the state thereof changed and the redundant column is activated. The address for each of the columns having a lower position than the defective column is incremented by one. The output of each of the columns is input to individual shift bits of a serial shift register (42), each shift bit having a normally open switch (44) associated therewith. Closure of the switches (44) bypasses the bit. A redundant shift bit R in the serial shift register (42) has a normally closed switch (45) associated therewith to bypass it in the normal mode. When a defective column is replaced, the associated shift bit has the switch (44) closed to bypass that shift bit and the switch (45) open.