Pipelined digital signal processor using a common data and control bus

Abstract

A pipelined digital signal processor includes a common data and control bus (101) and a source (100,105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-L,M,N and IR-S,T) receive a single instruction (i.e., I.sub.i) during each processor cycle for controlling all processing subsections (112, 115, 116) operations. During each processor cycle, each processing subsection (i.e., 112) performs an operation relating to a different expression than the other processing subsections (i.e., 115 or 116) are performing during that processor cycle. All of the operations controlled by the single instruction (i.e., I.sub.i) are executed during a single processor cycle. The common bus is time-shared during every processor cycle for transferring the single instruction from the source to the control circuits, for transferring data words from the source to the arithmetic section and for transferring the resultant data word from the arithmetic section to the destination.