The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 1986

Filed:

Dec. 15, 1983
Applicant:
Inventor:

Keizo Aoyama, Yamato, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307268 ; 307360 ; 307517 ; 307555 ; 307550 ; 307263 ;
Abstract

The present invention reduces rising and/or falling time delay of digital signals on poly-silicon layer wiring lines in semiconductors. Specific points of a network are fed with positive or negative voltage from a power source immediately after the initial rise and/or fall of the digital signals, and the potential at the specific point is rapidly pulled up or pulled down toward the source voltage. The pulling by the power source voltage is stopped when the potential reaches a specified value, and the pull-up or pull-down does not prevent subsequent operations. The signals reform or restore a square wave shape to the digital signals. The circuit includes a positive feedback circuit and a positive feedback cut-off circuit, each comprising an inverter and a transistor.


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