Circuit using slow sampling rate a-d converter which provides high

Abstract

The disclosure relates to a circuit using a relatively inexpensive relatively slow sampling rate A-D converter which provides resolution which is far superior to that obtained normally from the A-D converter being used. This is accomplished by providing a variable delay circuit wherein the delay is controllable. The maximum delay of the delay circuit is matched to the sampling rate of the A-D converter being used. The delay is then varied so that trigger pulses for commencing a sampling cycle are commenced at different points along the wave or information signal being sampled so that, after several different amounts of delay have been provided to information initiating triggering pulses, the information signal will have been sampled at various points therealong to provide the higher degree of resolution required while still using a relatively inexpensive slow sampling rate A-D converter.