Semaphore for memory shared by two asynchronous microcomputers

Abstract

An improved semaphore is described that arbitrates the access of a memory shared by first and second microcomputers operating asynchronously at the same speed or at different speeds. The semaphore includes a semaphore flip-flop producing a binary semaphore signal indicating whether or not the semaphore is owned, and an ownership flip-flop producing a binary ownership signal indicating which of the first or second microcomputers previously owned the semaphore. First gating circuitry decodes control signals from the first microcomputer and generates a read or write pulse signal. The read pulse signal from the first gating circuitry loads the semaphore signal and ownership signal into first and second flip-flops, respectively, whose outputs are applied to the data bus of the first microcomputer. Second gating circuitry decodes control signals from the second microcomputer and generates a read or write pulse signal. The read pulse signal from the second gating circuitry loads the semaphore signal and ownership signal into third and fourth flip-flops, respectively, whose outputs are applied to the data bus of the second microcomputer. If the first and second microcomputers access the semaphore simultaneously, access is granted to the second microcomputer since the output of the third flip-flop resets the first flip-flop to deny access to the first microcomputer.