Integated circuit memory

Abstract

An integrated circuit memory is disclosed having a power switch circuit which, in response to an enable signal, initially addresses a plurality of rows of memory elements during an initial pre-enable condition and which subsequently places the memory in the full enable condition to allow the address signal to address only a selected one of the plurality of memory elements. During a standby mode the rows of conductors coupled to the rows of memory elements are at a relatively 'high' voltage potential charging the large capacitance between the rows of conductors and a grounded substrate on which such conductors are formed. To address a particular row conductor and hence the memory elements coupled thereto during the enable mode, such row conductor must be coupled to ground potential. With the arrangement described above, by addressing a plurality of the addressed rows of conductors during the initial pre-enable condition, the relatively 'high' voltage on the plurality of rows of conductors is coupled to ground potential thereby more effectively and more rapidly discharging the voltage on the plurality of the addressed rows of conductors to reduce the effect of the capacitance, and hence the response time, of the memory circuit to the enable signal.