The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 1986

Filed:

Oct. 08, 1985
Applicant:
Inventors:

Akihiko Ito, Kawasaki, JP;

Tadahiro Saito, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 42 ; 357 43 ; 357 51 ; 357 68 ;
Abstract

A semiconductor device including a plurality of CMOS (Complementary Metal Oxide Semiconductor) elements, each comprised of a conventional source region, a drain region, and a diffusion region located adjacent to source and drain elements, and each driven by a power source. A first conductor and a second conductor, which are newly introduced in the present device, are physically independent from each other. The first conductor is connected between the power source and the source region. The second conductor is connected between the power source and the diffusion region.


Find Patent Forward Citations

Ito, Akihiko. (1986). Cmos circuit with separate power lines to suppress latchup (U.S. Patent No. 4591895). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4591895

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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