The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 1986

Filed:

Feb. 28, 1983
Applicant:
Inventors:

Thomas R Anderson, Tucson, AZ (US);

Howard L Skolnik, Tucson, AZ (US);

Bruce C Trump, Tucson, AZ (US);

Assignee:

Burr-Brown Corporation, Tucson, AZ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; G06G / ;
U.S. Cl.
CPC ...
307310 ; 307490 ; 3072 / ; 307243 ;
Abstract

A plurality of input stages having their outputs connected to provide differential currents to a load. When a bias current flows through a selected one of the input stages, the differential currents are provided in response to a differential signal provided to the selected stage. The input stages are each comprised of a pair of emitter-coupled transistors. Resistors are connected in series with the emitters of the transistors and the bias current is directly proportional to absolute temperature. The resistors may be adjusted to cause the offset voltages of the input stages to substantially equal zero at all temperatures.


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Anderson, Thomas. (1986). Multiple input port circuit having temperature zero voltage offset bias (U.S. Patent No. 4591740). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4591740

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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