The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 1986
Filed:
Aug. 31, 1984
Meir Gershenson, St. Paul, MN (US);
Sperry Corporation, New York, NY (US);
Abstract
In an improvement to the Selective Non-Anodizing Process (SNAP) an anodizable layer, nominally 100 nm of aluminum, is deposited on top of a 300 nm niobium--6 nm silicon--30 nm niobium tri-layer upon a substrate of oxidized silicon. The structure is then masked with photoresist and etched with an (aluminum) etchant, nominally phosphoric plus acetic plus nitric acid, which is selective to etch aluminum but not niobium. The structure, now containing a hard layer of aluminum plus an uppermost layer of photoresist over the regions where Josephson junctions will be formed, is then anodized by voltage ramping from 0 to 50 volts each 10 seconds in a saturate solution of ammonium penta borate in an equal solution of ethylene glycol and water. Both the uppermost niobium of the tri-layer and the aluminum are anodized save where protected by the photoresist. A protective insulator layer, nominally silicon mono oxide, is deposited by sputtering after which the mask of photoresist over aluminum is removed by the lift-off technique etching both anodized and remaining non-anodized aluminum. To the well-defined islands of niobium in a plane of anodized niobium, upper contact electrodes are formed by conventional deposition, photo lithographic, and etching techniques. This method so fabricating Josephson junction devices well-protects and defines the junctions under development while simultaneously reducing and simplifying the number of steps required in the patterning of the insulator layer.