The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 1986
Filed:
Feb. 08, 1985
Gregory J Cosimini, St. Paul, MN (US);
David S Lo, Burnsville, MN (US);
Lawrence G Zierhut, Burnsville, MN (US);
Sperry Corporation, New York, NY (US);
Abstract
The memory system incorporates a memory element storing binary digital data in the presence, vel non, of a Y-domain cross-tie. The memory element has a planar contour that is substantially symmetrical about a longitudinal axis and that has edge portions that are nowhere perpendicular or parallel to the longitudinal axis. A stabilizing magnetic field applied perpendicular to the longitudinal axis and in the plane of the memory element forms a first Neel wall along the longitudinal axis and causes the magnetization in the memory element to be formed into first and second domains on opposite sides of the Neel wall. When a writing magnetic field oriented in the plane of the memory element and perpendicular to the longitudinal axis but opposite to the stabilizing magnetic field orientation is coupled to the memory element, there is formed in the memory element a third domain separated from the first and second domains by second and third Neel walls having a join with one end of the first Neel wall. The first, second and third Neel walls form a 'Y'. Because of the nature of this third domain having its magnetization oriented in a direction parallel to the readout current caused to pass through the memory element, it produces a significantly greater difference in the readout signal between the readout of a stored 1 and a stored 0 than that achieved with the prior art cross-tie wall memory element.