The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 1986

Filed:

Sep. 24, 1984
Applicant:
Inventor:

Peter S Bernardson, Tempe, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
3403 / ; 3403 / ; 364746 ;
Abstract

In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue number signals {m1,m2,m3} to associated analog signals r(m1,m2,m3), and that does not require memory devices, comprises the steps of generating a pair of binary signals that are the sum and difference of the residue numbers m1 and m3, bit shifting these sum and difference signals by inserting 2n-1 and n-1 binary 0's as less significant bits thereof, and summing these bit shifted signals modulo p1*p3 to produce a two dimensional binary signal r(m1,m3). A correction signal is generated by modulo p2=2.sup.n summing the n less significant bits of the signal r(m1,m3 ) and the negative of the residue signal m2 to produce a second difference signal, bit shifting this second difference signal by inserting 2n binary 0's as less significant bits thereof and subtracting the second difference signal from this bit shifted signal to produce the correction signal. The signal r(m1,m3) and the correction signal are summed for producing a binary representation r(m1,m2,m3) of a given residue number {m1,m2,m3} . This binary signal is converted to the corresponding analog signal in a standard D/A converter. In a preferred embodiment, apparatus for performing the modulo p1*p3 summation is implemented with combining circuits that may be all standard binary adders so that all of the combining is done with standard binary adders and that no memory devices are required to perform the desired residue to binary conversion.


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