The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 1986

Filed:

Jul. 30, 1981
Applicant:
Inventor:

Shinji Morozumi, Suwa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G / ; G02E / ; H01L / ;
U.S. Cl.
CPC ...
350334 ; 340784 ; 350333 ; 357 237 ;
Abstract

An active matrix assembly for a liquid crystal display device utilizing an MIS (metal-insulator-semiconductor) transistor array is provided. The active matrix assembly includes a transparent substrate, a first thin layer of silicon disposed thereon, an insulating film on the first silicon layer and a second thin layer of silicon disposed on the insulating film. The layers are selectively etched for forming a gate and the silicon layers are doped for forming a MOS transistor for a display element of the device. The two silicon layers and insulating material intersect to form capacitors with the upper electrode of the storage capacitor being the driving electrode for the liquid crystal. An active matrix assembly constructed and arranged in accordance with the invention permits 90 percent or more of incident light coming from above to pass therethrough. Use of such a transparent substrate in an active matrix liquid crystal display device permits utilization of a transparent liquid crystal drive, such as the field effect type liquid crystal for providing a maximum degree of contrast. Operation of the device with peripheral drive circuits for the gate lines and data lines including non-inverting rationless shift registers formed in the same manner as the active matrix permits a substantial reduction in power consumption due to reduced parasitic capacitance.


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