Delayed monostable multivibrator

Abstract

A buffer comparator receives input pulses and produces buffer output signals that drive first and second output comparators arranged to operate as an amplitude-sensitive logic circuit that produces a high level output signal when and only when the internal driving signals have an amplitude between first and second threshold levels. In one embodiment, the output of the buffer comparator is applied directly to the non-inverting input terminal of the first logic circuit comparator and through a low resistance resistor to an R-C network and the inverting terminal of the second logic circuit comparator. The remaining input terminals on the logic comparators are connected to a multiple voltage divider that provides lower and upper threshold voltages to the respective comparators. An input pulse applied to the buffer comparator initiates an internal driving signal that charges the capacitor in the R-C network exponentially. While the voltage on the capacitor rises between the lower and upper threshold levels the logic comparators produce a high level output signal. When the input signal terminates, the low resistance resistor reverses the ordinary switching sequence of the logic comparators and prevents the formation of an output pulse at this time. A second embodiment of the invention dispenses with the means to reverse the ordinary switching sequence during discharge of the capacitor in the R-C network and thus provides a second positive-going output pulse at this time.