The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 1986
Filed:
Jun. 21, 1984
Mark S Birrittella, Phoenix, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A monolithically integrated memory cell having an improved clamped diode load is provided for improving write pulse width and write recovery times. A pair of latchable cross-coupled multi-emitter NPN transistors have a first emitter connected to a stand-by current drain line, and a second emitter coupled to a first bit line and a second bit line, respectively. The base of each transistor is cross-coupled to the collector of the other transistor. The base of each transistor is further coupled to the select line by a PNP transistor. The base of each PNP transistor is coupled to the collector of the respective cross-coupled transistor and is further coupled to the select line by a diode connected NPN transistor. The architecture of the diode connected NPN transistor in the chip prevents substantial stored charge buildup in the epi layer resulting in a lower voltage margin than previously known PN diode or PNP transistor loaded cells, and a higher voltage margin than the previously known Schottky diode loaded cell without the disturb sensitivity.