Insulated-gate field-effect transistors

Abstract

An insulated-gate field-effect transistor which may be of a vertical power D-MOS type includes surface-adjacent source and emitter regions surrounded in a semiconductor body by a surface-adjacent second region of opposite conductivity type. A third region adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of these second and third regions is located in a main current path from the source region to a drain of the transistor, and an insulated gate, which may be of metal-silicide, capacitively controls a conductive channel at least in this part of the second region. The emitter region is located at a side of the source region remote from the channel part and is separated therefrom by an intermediate part of the second region. The source region is electrically connected to this intermediate part, for example by a short-circuiting metal-silicide layer. A resistive current path in the second region is present below the emitter region and extends from this intermediate part to a further part of the second region which is electrically connected to the emitter region, for example by a short-circuiting metal-silicide layer. A source electrode is electrically connected to this further part so as to be electrically connected via the resistive current path to the source region. The emitter region serves to modulate the conductivity of the third region and thus reduce the drain series resistance of the transistor, by charge-carrier injection from the intermediate part when the source-drain current along the resistive current path is sufficient to forward-bias the intermediate part with respect to the third region.