The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 1986
Filed:
Dec. 28, 1982
Robert J Proebsting, Plano, TX (US);
Donald R Dias, Carrollton, TX (US);
Mostek Corporation, Carrollton, TX (US);
Abstract
A dynamic load circuit (34) selectively applies a high voltage state to a circuit node (42). A clock signal is coupled to a first node (54) and the inverse of the clock signal is coupled to a second node (60). Isolation transistors (50, 70) are controlled by the voltage level at the circuit node (42) to isolate the clock signals from the first and second nodes (54, 60) when the circuit node (42) is at a low voltage state. A high voltage signal V.sub.pp is coupled through a transistor (58) to the first node (54). The voltage at the first node (54) is coupled through a transistor (56) to the circuit node (42). The circuit node (42) is further coupled through transistors (62, 64) to the second node (60). The application of the alternating positive transistions of the clock and inverse clock signal cause the circuit (34) to apply a progressively increasing voltage to the circuit node (42). The dynamic load circuit (34) functions even if the threshold voltages of the high voltage transistors therein are almost as high as the supply voltage.