The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 1986
Filed:
Dec. 07, 1983
Applicant:
Inventors:
Doyle V McAlister, Pflugerville, TX (US);
Richard D Crisp, Beaverton, OR (US);
Assignee:
Motorola, Inc., Schaumburg, IL (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307475 ; 307452 ; 307481 ; 307246 ; 307269 ; 307579 ;
Abstract
A buffer circuit is provided for buffering an input clock signal having TTL voltage levels to provide an output clock signal having MOS voltage levels. A reference voltage portion provides an accurate bias voltage to a first node. A voltage translation portion is coupled between an input and the first node. An inverter portion has a first input connected to the first node, a second input for receiving the input clock signal, and an output for providing the output clock signal. A clamping portion is connected to the first node to minimize the bias voltage potential.