The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 1986

Filed:

Aug. 25, 1983
Applicant:
Inventor:

Tatsumi Hiramoto, Machida, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B / ;
U.S. Cl.
CPC ...
1566 / ;
Abstract

Disclosed herein is a process for forming a singlecrystalline silicon layer by heating a wafer having a starting silicon layer of amorphous or polycrystalline silicon on the singlecrystalline silicon substrate, in accordance with the epitaxial growth technique. The process comprises providing a heat source comprising a plurality of tubular lamps provided in a parallel second plane above a first plane in which the wafer is placed; lighting the tubular lamps to radiate their light to the wafer so as to hold the starting silicon layer at 1100.degree.-1400.degree. C. for 4 seconds or longer; and then, radiating light from a specific lamp to a portion of the starting silicon layer of the wafer where the temperature of the portion of the starting silicon layer is raised to 1410.degree.-1480.degree. C. and to form a narrow molten region and forming the same narrow molten regions successively one after another in the wafer. The above process can convert the starting silicon layer to a singlecrystalline silicon layer in a relatively short period of time and without danger of damaging the wafer.


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