Digital programmable packet switch synchronizer

Abstract

A digital programmable packet switch synchronizer receives a digital input data stream which includes a unique digital word. The unique digital word is stored in the synchronizer in a random access memory. A group of the most recently received data bits are stored in memory along with a blanker bit for each data bit. The blanker bit determines the valid or invalid status of the data bit. During each bit period of the incoming data stream, the stored data bits are serially compared with the stored unique word. A count is made of the number of noncomparisons between the stored data bits and the stored unique word bits when the data bit is valid. If the number of noncomparisons does not exceed a programmed error limit, an output signal is generated to indicate detection of the unique word. A similar count is carried out for detection of the inverse to the unique word. The number of invalid blanker bits for the data bits is also counted and if this count exceeds a programmed limit, the detection of the unique word is inhibited. When the positive of the unique word is detected, the incoming data is transmitted to an output terminal with a positive logic sense. But if the inverse of the unique word is detected, the incoming data is inverted and transmitted to the output terminal. In either case, the incoming data is transmitted to the output terminal with the correct polarity.