Clocking mechanism for multiple overlapped dynamic programmable logic

Abstract

A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit includes a plurality of dynamic programmable logic arrays for individually producing different ones of the control words. Each such control word includes a strobe field which is coded to identify a programmable logic array other than the one which produced it. The control unit also includes control circuitry responsive to the control words for producing the control point signals for successive machine control cycles. The control circuitry includes circuitry responsive to the strobe field in each control word for producing a strobe signal for selecting the next programmable logic array to supply a control word to the control circuitry. This control unit further includes clocking circuitry resposive to the strobe signals produced by the control circuitry for producing clocking signals for the dynamic programmable logic arrays. Such clocking circuitry includes only combinatorial logic circuitry for producing the clocking signals.