The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 1986
Filed:
Jul. 01, 1983
Alan S Bass, Mesa, AZ (US);
Shi-Chuan Lee, Mesa, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A macrocell array is provided wherein a plurality of cells, each having a plurality of semiconductor devices interconnected for providing logic functions, are selectively interconnected to one another and to input/output pads by a plurality of horizontal and vertical routing channels in one or more metallization layers. An on-chip diagnostic circuit is provided for diagnosing a plurality of serially connected latches, or flip-flops, in real time. A first logic gate has inputs adapted to receive a data signal and a data enable signal for inputting data into the latches. A second logic gate has inputs adapted to receive a shift-data-in signal and a shift enable signal for shifting the data through the latches. A third logic gate has inputs adapted to receive a hold signal and an output of a first of the plurality of serially connected latches for capturing the states in each of the latches at a given time. A fourth logic gate has inputs adapted to receive a complement enable signal and an output of the first latch for allowing desired test data to simultaneously appear at all the latches under test.