The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 1986
Filed:
Mar. 10, 1983
Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki, JP;
Abstract
An apparatus divides one element .alpha..sup.i of a Galois field GF(2.sup.m) by another element .alpha..sup.j of the field. Divider data .alpha..sup.j are supplied to one of the first linear shift registers and to the other first linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. Simultaneously, dividend data .alpha..sup.i are supplied to one of the second linear shift registers and to the other second linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. '1' detector circuits are connected to the outputs of the first linear shift registers, respectively. The first linear shift registers and the second linear shift registers are shifted several times until any '1' detector circuit detects '1' in response to output signals from a 2-input AND gate. When '1' is detected, a NOR gate supplies a signal of logical '0' to the AND gate, whereby the AND gate stops supplying output signals. 2-input AND circuits are connected at one input terminal to the outputs of the '1' detector circuits and at the other input terminal to the outputs of the second linear shift registers. The AND circuit connected to the '1' detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division .alpha..sup.i -.alpha..sup.j, are delivered through an OR circuit.
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