Linear codec with dual divider

Abstract

Disclosed is a charge redistribution codec employing a two capacitor network for developing a progression of reference voltages having a binary relationship to each other for each analog input sample to be encoded. Linear encoding of input samples is achieved with the use of two such charge redistribution networks, with one developing positive reference voltages and the other developing negative reference voltages. Analog input samples are placed in an encoding capacitor and based on the polarity of the voltage across the capacitor either a positive or a negative charge is added iteratively to the capacitor in the direction of driving the voltage across that capacitor to zero. A code is developed by assigning at each iteration one value to an output code bit when a positive voltage is added and the opposite value to the bit when a negative voltage is added. Chord-law encoding is achieved in a similar manner except that the output code includes a sign bit, a chord count and a linear code for describing the signal within the chord. Operationally, as with linear encoding two reference voltage generating circuits are employed to provide the positive and negative reference voltages. In addition, means are provided for adding an offset voltage to increase the magnitude of the input sample for assigning a sign bit based on the initial polarity of the input sample and for chord counting.