The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 1986
Filed:
Nov. 30, 1984
Fujitsu Limited, Kanagawa, JP;
Abstract
A method for fabricating a wafer for a dielectric isolation (DI) integrated circuit device is provided, wherein the substrate of the wafer, comprises portions of polycrystalline silicon positioned beneath regions for electrical elements, namely, 'islands', and portions of single crystal silicon are positioned in other areas of the wafer such as scribing regions, peripheral regions and contact regions. The single crystal portions of the substrate are grown during its fabricating steps by exposing surfaces of an original substrate of single crystal silicon, before the deposition of silicon onto the original substrate, by removing a dielectric isolation layer over the predetermined regions to be exposed. The single crystal silicon portions of the wafer provide various advantages for subsequent mechanical processing of the wafer such as shaping and rounding of the peripheral region and the scribing of the wafer into dice.