The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 1986
Filed:
Apr. 26, 1985
Applicant:
Inventors:
Mitsuo Morihisa, Nara, JP;
Hideyuki Akao, Osaka, JP;
Assignee:
Sharp Kabushiki Kaisha, Osaka, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364900 ; 307475 ; 365189 ;
Abstract
An interface circuit is disposed between an NMOS random access memory and a PMOS central processor unit in order to ensure accurate data transfer therebetween. The interface circuit includes a pull-up system for pulling up a signal transmission line to a desired voltage level. The pull-up system is energized when the data signal is transferred from the NMOS random access memory into the PMOS central processor unit. The pull-up operation is not conducted when the data signal is transferred from the PMOS central processor unit into the NMOS random access memory.